What data types can be synthesis in VHDL

You simply need to use VHDL-2008.

Q <= 8D"98";

will work just fine.

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I read VHDL tutorial but are confused in some data types. I found there are a lot of data types in VHDL, it is not easy to remember all of them.

I think only some of them are commonly used, these can be sythesised, will be most important. So I wonder anyone can give a small conclusion:

1. What are commonly used data types in VHDL?

2. What data types can be sythesised?

I have another question is what format can I assign value to STD_LOGIC_Vector? I try it in Quartus, if I define:

Q : buffer STD_LOGIC_Vector (7 downto 0);

I can only assign value to it like:

Q<=B"1000_0000";

Q<=X"AA";

Why do I have to use double quotes? I even can't assign it with decimal, if I wrote as:

Q<="98";

It reports error, how can I assign it with decimal&#65311;

Thanks very much.

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