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Altera_Forum's avatar
Altera_Forum
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13 years ago

What data types can be synthesis in VHDL

I read VHDL tutorial but are confused in some data types. I found there are a lot of data types in VHDL, it is not easy to remember all of them. I think only some of them are commonly used, the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Another question I have is: if I assign a value to a signal, variable, or port, does the value have to have double quote no matter what type they are?