Honored Contributor
Honored ContributorHi,
supported data types are listed in QII Help, referring to common VHDL standard libraries. Assuming you use IEEE.numeric.std, the data types are listed e.g. in http://www.csee.umbc.edu/portal/help/vhdl/numeric_std.vhdl. Thus you can assign (to the 8Bit vector) either binary "10101010", hexadecimal x"AA" or octal (something I never seen any practical implementation so far). The double quotes are VHDL syntax - that's why you have to use them... :-) Additionally the std_logic_vector is just a "collection of bits" - if you intend to do arithmetics or comparisons, you have to be careful about the MSB (being MSB of value or sign). Thus in numeric_std your's Q would be defined as q : signed(7 downto 0) with MSB = sign or q : unsigned(7 downto 0) with MSB = MSB... If you want to assign a decimal, you have to use a type conversion function to specify the decimal value "98" being a integer and to initialize the conversion in 8Bit Binary, i.e. q <= std_logic_vector(98) q <= signed(98) q <= unsigned(98) depending on definition of "q"... And well.. as VHDL describes real hardware, thus binary representations reflect hardware realization best, while decimal integers are the numbers humans are used to... :-) Contrary to some other languages there is less "implicit type conversion" implemented in VHDL. On first hand this may be annoying as you need to do more typing but to be honest this prevents the common mismatch between your intended definition and the "compiler's good guess" what might have been your intention. While the interpretation is normally written in the messages, do you really read carefully all messages and check, if the "good guess" matches your intention..?
