What data types can be synthesis in VHDL

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Another question I have is: if I assign a value to a signal, variable, or port, does the value have to have double quote no matter what type they are?

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I wrote some code below, in the spirit of VHDL-2008 and defining the constant in an easier way. To explicitly answer your question, if you use std_logic_vector, unsigned, or signed type, you need to explicitly use double quotes in defining the constant value in VHDL. This is part of the VHDL language specification.

The code below uses integer. The definition of the constant is simple.

library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity signed_adder is 
Port (
     clk   :   in std_logic;
      rst   :   in std_logic;
      Q     :   out std_logic_vector(7 downto 0)
      );
      
architecture RTL of signed_adder is 
signal   qx : integer range 0 to 255;
CONSTANT resetValue := integer := 12;
begin
process(all) begin
   if rst then
      qx <= 12;
    elsif rising_edge(clk) then
      qx <= qx + 1;
    end if;
end process;
Q <= std_logic_vector(to_signed(qx,8));
end RTL;