Viewing signal lines beside ports during simulation

Question

Hello!

I would like to be able to see during a functional simulation signals declared in an architecture. Up to now, I can only see the ports declared in the entity but not the signals declared in an architecture even after having iinserted them in the signals assigment list.

Because of that, I have to make my simulations with another software. I would lie to be able to see all signals types and not only entity-ports on the signal viewing graph.

Taking the following snipet below, I would like also to be able to view sig_a and sig_b signals declared in the architecture; but I'm not able to vieuw those signals even I've inserted them. Could you please show me how to do that with Quartus 2 version 6.1?

Regards,

library ieee;

use ieee.std_logic_1164.all;

entity any is

port(

x : in std_logic;

y : out std_logic

);

end any;

architecture any_arch of any is

signal sig_a, sig_b : std_logic;

begin

end any_arch;

altera_forum · Answer

I haven't tried the "keep" synthesis attribute specifically for functional simulation, but it might be what you need if your signals are combinational.  If the signals are registers, they might be optimized out in a way you can control with another logic option or synthesis attribute like "preserve".  The "Quartus II Integrated Synthesis" chapter of Quartus handbook Volume 1 has information about the available synthesis attributes.  signal sig_a, sig_b : std_logic;
attribute keep: boolean;
attribute keep of sig_a: signal is true;
attribute keep of sig_b: signal is true;   If the signals are only for simulation purposes and have no fan-out, then see "Noprune Synthesis Attribute/Preserve Fanout Free Node" in the same handbook chapter.

altera_forum · Answer

Hi Brad,

First, thank you for replying. I've included the lines of code you've proposed, but still I'm unable to view those signals declared in the architecture. Quartus keep showing me only the entity port signals, even when I did not inserted them to be viewed. With other couple of softwares i'm forced to use in order to be able to view those signal traces, they become parts of the signal list automatically when the VHDL code is compiled. If I want them to be viewed, all I have to do is to insert them in the signal list. With Quartus, even the simplest task seems very complecated to be achieved.

Thanks a lot for trying to help.

Regards,

altera_forum · Answer

I created the attached vhdl_sim_example.zip test case based on your code example.

Do sig_a and sig_b drive fan-out that doesn't get synthesized away? If they have no direct fan-out or if their fan-out gets synthesized away, you need the noprune attribute I mentioned. In my test case, sig_b has no fan-out. The handbook says the noprune attribute is for a register with no fan-out, and I had to make sig_b be a register to get the attribute to work for my test case. I used the noprune attribute in the with_synthesis_attributes revision (select it at "Project --> Revisions").

In my test case, sig_a is a combinational node that does not exist as a distinct node after synthesis. (Its function is contained within a LUT that also implements other logic.) Even so, my functional simulation showed sig_a without my bothering with the keep attribute. If your sig_a is combinational, I suspect it's still possible it wouldn't survive the part of synthesis that creates the nodes available for functional simulation.

If sig_a and sig_b are registers, you might need an attribute like preserve as I said before. The keep attribute is only for combinational nodes.

If you are using a .vwf file for simulation, did you insert sig_a and sig_b with the Node Finder so that you know the names are valid? This will make sure you will have the right hierarchy in the names. (My simple test case has no hierarchy.)

altera_forum · Answer

Hi Brad,

Thanks to you, I'm starting to understand how works QUARTUS. I've created a simple combinational circuit with internal signal lines that I was finally able to show up the signal viewer. To me, it's just a matter to understand how Quartus works and learn those new terms kike KEEP, NOPRUNE and the other thousands of those terms which are completely inexistant in all the softwares I've been using until present time and which are gonna strike me as long I'll be using Quartus.

Thanks for your time and your good help method.

Regards,

altera_forum · Answer

This might be a good time to mention some simulation caveats that apply to any FPGA design (not just Altera FPGAs). When you look at internal signals during simulation, synthesis for FPGAs can do things that make the behavior different from what you might expect from the source files.

This is especially true for combinational nodes where synthesis can do all sorts of valid things that make an internal node with a name similar to a name in a source file behave very differently from the source file signal. The keep attribute can help with this at the possible expense of an additional LUT in the design because your keep attribute prevented synthesis from doing some valid optimizations.

Even registered signals can behave differently from what you would expect from the source files. Synthesis can move the registers with respect to the logic before or after them to help with the timing performance. For a simpler change that affects simulation, synthesis can move an inversion before or after a register to help with logic optimizations.

I don't know how many of the synthesis optimizations affect functional simulation in the Quartus native simulator. Timing simulations will be subject to all these synthesis optimizations.

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Viewing signal lines beside ports during simulation

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