Viewing signal lines beside ports during simulation

I haven't tried the "keep" synthesis attribute specifically for functional simulation, but it might be what you need if your signals are combinational. If the signals are registers, they might be optimized out in a way you can control with another logic option or synthesis attribute like "preserve". The "Quartus II Integrated Synthesis" chapter of Quartus handbook Volume 1 has information about the available synthesis attributes.

signal sig_a, sig_b : std_logic;
attribute keep: boolean;
attribute keep of sig_a: signal is true;
attribute keep of sig_b: signal is true;