Viewing signal lines beside ports during simulation

I created the attached vhdl_sim_example.zip test case based on your code example.

Do sig_a and sig_b drive fan-out that doesn't get synthesized away? If they have no direct fan-out or if their fan-out gets synthesized away, you need the noprune attribute I mentioned. In my test case, sig_b has no fan-out. The handbook says the noprune attribute is for a register with no fan-out, and I had to make sig_b be a register to get the attribute to work for my test case. I used the noprune attribute in the with_synthesis_attributes revision (select it at "Project --> Revisions").

In my test case, sig_a is a combinational node that does not exist as a distinct node after synthesis. (Its function is contained within a LUT that also implements other logic.) Even so, my functional simulation showed sig_a without my bothering with the keep attribute. If your sig_a is combinational, I suspect it's still possible it wouldn't survive the part of synthesis that creates the nodes available for functional simulation.

If sig_a and sig_b are registers, you might need an attribute like preserve as I said before. The keep attribute is only for combinational nodes.

If you are using a .vwf file for simulation, did you insert sig_a and sig_b with the Node Finder so that you know the names are valid? This will make sure you will have the right hierarchy in the names. (My simple test case has no hierarchy.)