Viewing signal lines beside ports during simulation

This might be a good time to mention some simulation caveats that apply to any FPGA design (not just Altera FPGAs). When you look at internal signals during simulation, synthesis for FPGAs can do things that make the behavior different from what you might expect from the source files.

This is especially true for combinational nodes where synthesis can do all sorts of valid things that make an internal node with a name similar to a name in a source file behave very differently from the source file signal. The keep attribute can help with this at the possible expense of an additional LUT in the design because your keep attribute prevented synthesis from doing some valid optimizations.

Even registered signals can behave differently from what you would expect from the source files. Synthesis can move the registers with respect to the logic before or after them to help with the timing performance. For a simpler change that affects simulation, synthesis can move an inversion before or after a register to help with logic optimizations.

I don't know how many of the synthesis optimizations affect functional simulation in the Quartus native simulator. Timing simulations will be subject to all these synthesis optimizations.