Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Viewing signal lines beside ports during simulation

Hello! I would like to be able to see during a functional simulation signals declared in an architecture. Up to now, I can only see the ports declared in the entity but not the signals declared...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

You can replace the synthesis and timing analysis within Quartus flow with some 3rd party tool, but you can not run away from the place and route process which only provided by Altera through Quartus. Comparing ORCAD and Quartus compilation is like comparing apple and orange....each are doing totally different thing.