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Altera_Forum
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18 years ago

Viewing signal lines beside ports during simulation

Hello! I would like to be able to see during a functional simulation signals declared in an architecture. Up to now, I can only see the ports declared in the entity but not the signals declared...
Altera_Forum's avatar
Altera_Forum
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18 years ago

I don't know of any third-party EDA tools that Altera officially sanctions for FPGA compilation. Altera tries to make Quartus interact well with third-party tools for board layout, third-party synthesis (like Synplify and Precision), third-party simulation (like ModelSim), etc.