Viewing signal lines beside ports during simulation

Hi Brad,

First, thank you for replying. I've included the lines of code you've proposed, but still I'm unable to view those signals declared in the architecture. Quartus keep showing me only the entity port signals, even when I did not inserted them to be viewed. With other couple of softwares i'm forced to use in order to be able to view those signal traces, they become parts of the signal list automatically when the VHDL code is compiled. If I want them to be viewed, all I have to do is to insert them in the signal list. With Quartus, even the simplest task seems very complecated to be achieved.

Thanks a lot for trying to help.

Regards,