VHDL expression error ( different data width)

at least look here but you need care about these variables:

master_writedata <= "00000000" & fifo_data_out;

and check the widths.

24 + 8 = 32

16+8 = 24

Yes,

try

master_writedata <= ( INPUT_DATAWIDTH-1 DOWNTO 0 => fifo_data_out,      others => '0'); -- assign "fifo_data_out" to the LSB of "master_write_data"

I saw those zeros as Hex value......you are right.

Thanks :)

--- Quote Start ---

I saw those zeros as Hex value......you are right.

Thanks :)

--- Quote End ---

while applying user variable widths and other variable parameters is necessary for ips but for individual modules I don't not see it as needed and I have almost never seen any local parameterised modules to work if I change a parameter because of dependency and lack of testing.

I already noticed your fifo is actually fixed to 16 bits and the parameter is not used.

Hi mmTsuchi,

Your solution is more practical.

fifo_data_out is defined as

SIGNAL fifo_data_out				: STD_LOGIC_VECTOR(INPUT_DATAWIDTH-1 DOWNTO 0);

and I am getting this error on Quartus

--- Quote Start ---

Error (10476): VHDL error at ADC_Burst_Write_Master.vhd(193): type of identifier "fifo_data_out" does not agree with its usage as "std_ulogic" type

--- Quote End ---

How to work around it?

--- Quote Start ---

Hi mmTsuchi,

Your solution is more practical.

fifo_data_out is defined as

SIGNAL fifo_data_out                : STD_LOGIC_VECTOR(INPUT_DATAWIDTH-1 DOWNTO 0);

and I am getting this error on Quartus

How to work around it?

--- Quote End ---

I think that statement posted means bit by bit mapping. You better just use:

<= x"0000" & fifo_data_out;