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Altera_Forum
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12 years ago

VHDL expression error ( different data width)

Hello, I am not expert in VHDL, and I got stuck with this problem. In the original code 'fifo_data_out' was defined as 24 bit (INPUT_DATAWIDTH = 24) and the compilation was successful SI...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I saw those zeros as Hex value......you are right.

Thanks :)