VHDL expression error ( different data width)

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I saw those zeros as Hex value......you are right.

Thanks :)

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while applying user variable widths and other variable parameters is necessary for ips but for individual modules I don't not see it as needed and I have almost never seen any local parameterised modules to work if I change a parameter because of dependency and lack of testing.

I already noticed your fifo is actually fixed to 16 bits and the parameter is not used.