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Altera_Forum
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11 years ago

VHDL expression error ( different data width)

Hello, I am not expert in VHDL, and I got stuck with this problem. In the original code 'fifo_data_out' was defined as 24 bit (INPUT_DATAWIDTH = 24) and the compilation was successful SI...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi mmTsuchi,

Your solution is more practical.

fifo_data_out is defined as 


SIGNAL fifo_data_out				: STD_LOGIC_VECTOR(INPUT_DATAWIDTH-1 DOWNTO 0);

and I am getting this error on Quartus

--- Quote Start ---

Error (10476): VHDL error at ADC_Burst_Write_Master.vhd(193): type of identifier "fifo_data_out" does not agree with its usage as "std_ulogic" type

--- Quote End ---

How to work around it?