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Altera_Forum
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11 years ago

VHDL expression error ( different data width)

Hello, I am not expert in VHDL, and I got stuck with this problem. In the original code 'fifo_data_out' was defined as 24 bit (INPUT_DATAWIDTH = 24) and the compilation was successful SI...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

at least look here but you need care about these variables:

master_writedata <= "00000000" & fifo_data_out;

and check the widths.

24 + 8 = 32

16+8 = 24