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Altera_Forum
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11 years ago

VHDL expression error ( different data width)

Hello, I am not expert in VHDL, and I got stuck with this problem. In the original code 'fifo_data_out' was defined as 24 bit (INPUT_DATAWIDTH = 24) and the compilation was successful SI...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Yes,

try 

master_writedata <= ( INPUT_DATAWIDTH-1 DOWNTO 0 => fifo_data_out,      others => '0'); -- assign "fifo_data_out" to the LSB of "master_write_data"