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Altera_Forum
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11 years ago

VHDL expression error ( different data width)

Hello, I am not expert in VHDL, and I got stuck with this problem. In the original code 'fifo_data_out' was defined as 24 bit (INPUT_DATAWIDTH = 24) and the compilation was successful SI...
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Altera_Forum
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11 years ago

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Hi mmTsuchi,

Your solution is more practical.

fifo_data_out is defined as 


SIGNAL fifo_data_out                : STD_LOGIC_VECTOR(INPUT_DATAWIDTH-1 DOWNTO 0);

and I am getting this error on Quartus

How to work around it?

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I think that statement posted means bit by bit mapping. You better just use:

<= x"0000" & fifo_data_out;