VHDL and process : several sensivity signals

Where are you having the problem? in simulation or hardware? this code is not suitable for FPGAs, as multiple clocks are not allowed.

Why not post the code with the problem.

The situation you describe is not possible with the code snippet you posted - you need to post the whole code.

Thank you very much for your answer Tricky, I am having the problem in hardware :

CODE1 does the following :

- It sets a flag and reset a counter.

CODE2 does the following :

- If the flag is set, it increments a counter. When the counter reaches its maximum, it resets the counter and resets the flag. Then, we have to wait until CODE1 sets the flag to enter in CODE2.

The problem is that when I set "SIGNAL", the counter increases and decreases randomly around a random value : As if counter was constantly reset from CODE1.

Here is the code :

---------------------------

CODE1 :

flag <='1';

CODE2 :

if (flag = '1') then

if(counter < max) then

counter := counter + 1;

else

counter := 0;

flag <= '0';

end if;

end if;

---------------------------

But you've answered my question : multiple clocks (multiple "rising_edge" tests) are not allowed, which could explain such erratic behavior. I have to think of another way to implement my code.

Thank you again for your help.

I finally found a solution ! To whom it may help :

What I wanted to do (the following code DOES NOT work) :

process(CLK, SIGNAL)

begin

if rising_edge(SIGNAL) then

flag <='1';

end if;

if rising_edge(CLK) then

if (flag = '1') then

if(counter < max) then

counter := counter + 1;

else

counter := 0;

flag <= '0';

end if;

end if;

end if;

end process;

The solution I've found (the following code SEEMS to work) :

process(CLK, SIGNAL)

begin

if (SIGNAL='1' and flag = '0' ) then

flag <= '1';

flag2 <= '1';

elsif(SIGNAL='0') then

flag <= '0';

elsif rising_edge(CLK) then

if(flag2 = '1') then

-- CODE

flag2 = '0';

end if;

-- CODE

end if;

end process;

you are missing "flag" from the first code sensitivity list. This mean's you'll have a missmatch between the simulation and the actual code on hardware.

What you need to do is build an edge detector - simply register signal and compare it to the incoming value:

signal sig_r : std_logic;
process(clk)
begin
  if rising_edge(clk) then
    sig_r <= sig;
    
    if sig_r = '0' and sig = '1' then --check for rising edge of SIGNAL
      flag <= '1';
      
    else
        --etc
    end if;
  end if;
end process;