VHDL and process : several sensivity signals

I finally found a solution ! To whom it may help :

What I wanted to do (the following code DOES NOT work) :

process(CLK, SIGNAL)

begin

if rising_edge(SIGNAL) then

flag <='1';

end if;

if rising_edge(CLK) then

if (flag = '1') then

if(counter < max) then

counter := counter + 1;

else

counter := 0;

flag <= '0';

end if;

end if;

end if;

end process;

The solution I've found (the following code SEEMS to work) :

process(CLK, SIGNAL)

begin

if (SIGNAL='1' and flag = '0' ) then

flag <= '1';

flag2 <= '1';

elsif(SIGNAL='0') then

flag <= '0';

elsif rising_edge(CLK) then

if(flag2 = '1') then

-- CODE

flag2 = '0';

end if;

-- CODE

end if;

end process;