Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

VHDL and process : several sensivity signals

Hi, I have a problem with the following structure of process : process(clk, signal) begin if rising_edge(signal) then -- code1 end if; if rising_edge(clk) then ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

If it got to hardware, it would have actually used your code. If it did think there were actually 2 clocks, it would have caused and error.