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Altera_Forum's avatar
Altera_Forum
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11 years ago

VHDL and process : several sensivity signals

Hi, I have a problem with the following structure of process : process(clk, signal) begin if rising_edge(signal) then -- code1 end if; if rising_edge(clk) then ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Where are you having the problem? in simulation or hardware? this code is not suitable for FPGAs, as multiple clocks are not allowed.

Why not post the code with the problem.

The situation you describe is not possible with the code snippet you posted - you need to post the whole code.