VHDL and process : several sensivity signals

Thank you very much for your answer Tricky, I am having the problem in hardware :

CODE1 does the following :

- It sets a flag and reset a counter.

CODE2 does the following :

- If the flag is set, it increments a counter. When the counter reaches its maximum, it resets the counter and resets the flag. Then, we have to wait until CODE1 sets the flag to enter in CODE2.

The problem is that when I set "SIGNAL", the counter increases and decreases randomly around a random value : As if counter was constantly reset from CODE1.

Here is the code :

---------------------------

CODE1 :

flag <='1';

CODE2 :

if (flag = '1') then

if(counter < max) then

counter := counter + 1;

else

counter := 0;

flag <= '0';

end if;

end if;

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But you've answered my question : multiple clocks (multiple "rising_edge" tests) are not allowed, which could explain such erratic behavior. I have to think of another way to implement my code.

Thank you again for your help.