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Altera_Forum's avatar
Altera_Forum
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10 years ago

VHDL and process : several sensivity signals

Hi, I have a problem with the following structure of process : process(clk, signal) begin if rising_edge(signal) then -- code1 end if; if rising_edge(clk) then ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

you are missing "flag" from the first code sensitivity list. This mean's you'll have a missmatch between the simulation and the actual code on hardware.

What you need to do is build an edge detector - simply register signal and compare it to the incoming value: 


signal sig_r : std_logic;
process(clk)
begin
  if rising_edge(clk) then
    sig_r <= sig;
    
    if sig_r = '0' and sig = '1' then --check for rising edge of SIGNAL
      flag <= '1';
      
    else
        --etc
    end if;
  end if;
end process;