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Armando1989's avatar
Armando1989
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
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Very slow clock should be constraint as false path?

Hi there

Ive just created project in which 1200bps rs232 data is sampled and then loaded into 8 paralel registers to leds. All registers but the final latch are driven by 50MHz board, but set clk_enable siganl which is 1200Hz, avoiding as far as i could clock domain cross. It seems working fine based on simulations and timing results.

However my question is, basically quartus considers register on image a clock for sure:

however that clock is just the latch signal to the output registers and happens only 1200hz/11 at most because its only active when new rs232 8 bit data has been captured... I cannot create such a low "derived" clock on constraints as it says divide factor is out of range.

Should be considered false path between clk and output of Word registers?

Im not quite sure how to cover that constraint right now.

Thanks in advance

BR

Compilation
  • sstrell's avatar
    sstrell
    1 year ago

    The problem is that you are using DONE as a clock signal. It's not. You should just create combinatorial logic or better yet synchronize the loading of word with clk.

    always @(negedge clk) begin
   if (reset) begin
       word<=0;
   end
   else if (DONE && clk_enable) begin
       word<=tmp[7:0];
   end
end

10 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    You may be able to get away with false pathing it, but how is it coded?

    • Armando1989's avatar
      Armando1989
      Icon for Occasional Contributor rankOccasional Contributor
      1 year ago
      Hi ssteell thanks in advance
      Im not quite sure you mean with "how is it coded". If u need i can post verilog code for that module.
      Br
  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Yeah, I mean seeing how you coded the signal to understand its behavior.

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    The problem is that you are using DONE as a clock signal. It's not. You should just create combinatorial logic or better yet synchronize the loading of word with clk.

    always @(negedge clk) begin
   if (reset) begin
       word<=0;
   end
   else if (DONE && clk_enable) begin
       word<=tmp[7:0];
   end
end
    • Armando1989's avatar
      Armando1989
      Icon for Occasional Contributor rankOccasional Contributor
      1 year ago

      Hi

      Yep that did the trick, i guess is just apply same logic ive just being doing with clk_enable to maintain just clk 50MHz domain.

      One drawback i see using sclock enable method is: Capture window gets quite short and cannot be extended by more than one 50Mhz cycle, since your FSM is sampling 1200Hz data once at a time, u cannot extend capturing window ie: 2x50MHz clocks, as would sample more than 1 time each 1200Hz sample and FSM will missbehave.

      When have to sync 2 signals between fsm and capturing module as below, with that capturing window there is little space and hold time constraint gets worse of course. Below there is half 50MHZ clk 10ns. The reason of "50MHz negedge" for DONE is just to have room for the GO signal to set low just within one 50MHz clk :D.

      Thanks!

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    You could use a counter to keep track of a signal level for multiple clock cycles. Or you could use a multicycle timing exception to have the timing analysis extended an extra cycle if you can't change the design.

    • Armando1989's avatar
      Armando1989
      Icon for Occasional Contributor rankOccasional Contributor
      1 year ago

      Hi Sstrell

      1-"You could use a counter to keep track of a signal level for multiple clock cycles"-->that not sure how, my FSM is sampling the 1200baud data for each 1200Hz clock enable pulse (one 50MHz clock every 1200Hz) .

      2-"Or you could use a multicycle timing exception to have the timing analysis extended an extra cycle if you can't change the design"-->in my case as u see my capture window is half 50Mhz clock, FSM samples on rising edge and capturer on falling edge, so cannot apply multicycle between both modules.

      JFYI let u the simple FSM code, u can see what i mean.. For your porpossal might need to modify FSM increasing number of states it stays as GO=0 and GO=1, sampling several clock cycles like a sequence detector, ie: detect 2 zeroes triggers start bit then move to state RUN...?. Of course would need also to enlarge the clock enable width for the appropiate window... lets say... 4X50MHz clk´s each 1200Hz...

      Now FSM is just simple IDLE<-->RUN...

      As u see im just trying to learn and enhace, even timing is acceptable around 112MHz, slack is also ok...

      Thanks for your share and time in advance!.

      BR

      • FvM's avatar
        FvM
        Icon for Super Contributor rankSuper Contributor
        1 year ago
        Hi,
        some improvements suggested. Presume rs232 input data is asynchronous to FSM clock. Then a certain rate of FSM failure must be expected, worst case a non-recoverable transition to an illegal state. It's necessary to add a synchronizer register chain for data.