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Armando1989's avatar
Armando1989
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
Solved

Very slow clock should be constraint as false path?

Hi there Ive just created project in which 1200bps rs232 data is sampled and then loaded into 8 paralel registers to leds. All registers but the final latch are driven by 50MHz board, but set clk_en...
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  • sstrell's avatar
    sstrell
    1 year ago

    The problem is that you are using DONE as a clock signal. It's not. You should just create combinatorial logic or better yet synchronize the loading of word with clk.

    always @(negedge clk) begin
   if (reset) begin
       word<=0;
   end
   else if (DONE && clk_enable) begin
       word<=tmp[7:0];
   end
end
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
1 year ago

The problem is that you are using DONE as a clock signal. It's not. You should just create combinatorial logic or better yet synchronize the loading of word with clk.

always @(negedge clk) begin
   if (reset) begin
       word<=0;
   end
   else if (DONE && clk_enable) begin
       word<=tmp[7:0];
   end
end
Armando1989's avatar
Armando1989
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hi

Yep that did the trick, i guess is just apply same logic ive just being doing with clk_enable to maintain just clk 50MHz domain.

One drawback i see using sclock enable method is: Capture window gets quite short and cannot be extended by more than one 50Mhz cycle, since your FSM is sampling 1200Hz data once at a time, u cannot extend capturing window ie: 2x50MHz clocks, as would sample more than 1 time each 1200Hz sample and FSM will missbehave.

When have to sync 2 signals between fsm and capturing module as below, with that capturing window there is little space and hold time constraint gets worse of course. Below there is half 50MHZ clk 10ns. The reason of "50MHz negedge" for DONE is just to have room for the GO signal to set low just within one 50MHz clk :D.

Thanks!