Very slow clock should be constraint as false path?

The problem is that you are using DONE as a clock signal. It's not. You should just create combinatorial logic or better yet synchronize the loading of word with clk.

always @(negedge clk) begin
   if (reset) begin
       word<=0;
   end
   else if (DONE && clk_enable) begin
       word<=tmp[7:0];
   end
end