Verilog ROM code is not inferred as ROM block!!

http://www.altera.com/literature/hb/qts/qts_qii51007.pdf

See page 8.

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http://www.altera.com/literature/hb/qts/qts_qii51007.pdf

See page 8.

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I use similar to the code shown below. When I try to fit my design into different device it shows that number of block memory bits used is 0 !!! what should i do to make it recognize the ROM!

module sync_rom (clock, address, data_out);

input clock;

input [7:0] address;

output [5:0] data_out;

reg [5:0] data_out;

always @ (posedge clock)

begin

case (address)

8'b00000000: data_out = 6'b101111;

8'b00000001: data_out = 6'b110110;

...

8'b11111110: data_out = 6'b000001;

8'b11111111: data_out = 6'b101010;

endcase

end

endmodule

Sorry, I misunderstood - I thought your problem was that you were using too many registers. But your problem is actually that your ROM is so small that Quartus is fitting the ROM into a handful of registers instead of consuming a M9K memory with them.

In order to get Quartus to force it to use M9K, you need to set "Allow Any ROM Size for Recognition" as described on page 12-27 of the HDL coding guidelines previously linked to, and you need to correctly set the romstyle = "M9K" attribute. e.g.

   (* romstyle = "M9K" *) output reg   data_out;

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Sorry, I misunderstood - I thought your problem was that you were using too many registers. But your problem is actually that your ROM is so small that Quartus is fitting the ROM into a handful of registers instead of consuming a M9K memory with them.

In order to get Quartus to force it to use M9K, you need to set "Allow Any ROM Size for Recognition" as described on page 12-27 of the HDL coding guidelines previously linked to, and you need to correctly set the romstyle = "M9K" attribute. e.g.

   (* romstyle = "M9K" *) output reg   data_out;

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I have written a verilog code for a ROM:

module sync_rom (clock, address, data_out);

input clock;

input [3:0] address;

/* romstyle = "M9K" */ output reg [31:0] data_out;

always @ (posedge clock) begin case (address)

///// assign values to data_out

// 0: data_out = 32'haf123412;

endcase

end

endmodule

I have also tried to add /* romstyle = "M9K" */ but when I synthesize and tried to fit my design the number of block memory bits is zero!! and the registers are used!! How can I force the Quartus to synthesize my code as a ROM 16 x 32-bit. I have to mention that I have changed the settings for Synthesis and Analysis to recognize the ROM and RAM of any size!

Actually, I did this before and mentioned this on the first post. Please help :)

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Actually, I did this before and mentioned this on the first post. Please help :)

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Try the things I mentioned in the 4th post:

Did you change the "Allow Any ROM Size for Recognition" setting?

Did you change your code to correctly say (* romstyle = "M9K" *) ? Your pasted code is using Verilog comments, which won't do anything.

If you do these things, it will work (at least it works for me...)

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Try the things I mentioned in the 4th post:

Did you change the "Allow Any ROM Size for Recognition" setting?

Did you change your code to correctly say (* romstyle = "M9K" *) ? Your pasted code is using Verilog comments, which won't do anything.

If you do these things, it will work (at least it works for me...)

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Thanks alot for replying to my message. I really appreciate your help :)

YES I change the settings and use the parenthesis (* *) rather than /* */ and it still not showing memory bits used! I know it is strange but this is the truth. I solved it by creating ROM with single port in mega wizard and then I open the design file created automatically by Quartus, I copied the verilog code and pasted it in my verilog file (data read from mif file). When I compiled and synthesized the design, it shows the memory bits used :)

BUT when I try to fit the design on some devices (I tried Cyclone II, III and Stratix III) it fails although the number of logic elements and memory bits on the targeted device is enough. The message I have got "Design requires too many ram resources to fit in the selected device "!

for the ROM, I am using 4 modules represent ROM blocks (16 x 32-bit). So each ROM block is 512 bits with a total of 2,048 bits.

the total number of memory bits used in the design is 327,680 bits (modules is used many times in the design).

How can I solve this problem?

Most likely your problem is that each of your ROM instances which you hope would consume 512 bits is requiring either an entire M9K or one half of one M9K if the fitter successfully uses "Packed Mode" when fitting the ROMs together.

You can't really use "total bits" as an indicator of how much space you have remaining, because a design like yours could map very inefficiently and consume all of the M9K with very low total bit count. Look at the Fitter report in Fitter->Resource Section->Resource Usage Summary to get the high level number of M9K used/available.

You can read in some detail about memory resources in your device handbook (e.g. Cyclone III here http://www.altera.com/literature/hb/cyc3/cyc3_ciii51003.pdf with Packed Mode described on page 5).