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Try the things I mentioned in the 4th post:
Did you change the "Allow Any ROM Size for Recognition" setting?
Did you change your code to correctly say (* romstyle = "M9K" *) ? Your pasted code is using Verilog comments, which won't do anything.
If you do these things, it will work (at least it works for me...)
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Thanks alot for replying to my message. I really appreciate your help :)
YES I change the settings and use the parenthesis (* *) rather than /* */ and it still not showing memory bits used! I know it is strange but this is the truth. I solved it by creating ROM with single port in mega wizard and then I open the design file created automatically by Quartus, I copied the verilog code and pasted it in my verilog file (data read from mif file). When I compiled and synthesized the design, it shows the memory bits used :)
BUT when I try to fit the design on some devices (I tried Cyclone II, III and Stratix III) it fails although the number of logic elements and memory bits on the targeted device is enough. The message I have got "Design requires too many ram resources to fit in the selected device "!
for the ROM, I am using 4 modules represent ROM blocks (16 x 32-bit). So each ROM block is 512 bits with a total of 2,048 bits.
the total number of memory bits used in the design is 327,680 bits (modules is used many times in the design).
How can I solve this problem?
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