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Altera_Forum
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11 years ago

Verilog ROM code is not inferred as ROM block!!

I have written a verilog code for a ROM: module sync_rom (clock, address, data_out); input clock; input [3:0] address; output [31:0] data_out; reg [31:0] data_out;...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Sorry, I misunderstood - I thought your problem was that you were using too many registers. But your problem is actually that your ROM is so small that Quartus is fitting the ROM into a handful of registers instead of consuming a M9K memory with them.

In order to get Quartus to force it to use M9K, you need to set "Allow Any ROM Size for Recognition" as described on page 12-27 of the HDL coding guidelines previously linked to, and you need to correctly set the romstyle = "M9K" attribute. e.g. 


   (* romstyle = "M9K" *) output reg   data_out;