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Sorry, I misunderstood - I thought your problem was that you were using too many registers. But your problem is actually that your ROM is so small that Quartus is fitting the ROM into a handful of registers instead of consuming a M9K memory with them.
In order to get Quartus to force it to use M9K, you need to set "Allow Any ROM Size for Recognition" as described on page 12-27 of the HDL coding guidelines previously linked to, and you need to correctly set the romstyle = "M9K" attribute. e.g.
(* romstyle = "M9K" *) output reg data_out;
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I have written a verilog code for a ROM:
module sync_rom (clock, address, data_out);
input clock;
input [3:0] address;
/* romstyle = "M9K" */ output reg [31:0] data_out;
always @ (posedge clock) begin case (address)
///// assign values to data_out
// 0: data_out = 32'haf123412;
endcase
end
endmodule
I have also tried to add /* romstyle = "M9K" */ but when I synthesize and tried to fit my design the number of block memory bits is zero!! and the registers are used!! How can I force the Quartus to synthesize my code as a ROM 16 x 32-bit. I have to mention that I have changed the settings for Synthesis and Analysis to recognize the ROM and RAM of any size!
Actually, I did this before and mentioned this on the first post. Please help :)
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