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Altera_Forum's avatar
Altera_Forum
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11 years ago

Verilog ROM code is not inferred as ROM block!!

I have written a verilog code for a ROM: module sync_rom (clock, address, data_out); input clock; input [3:0] address; output [31:0] data_out; reg [31:0] data_out;...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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Actually, I did this before and mentioned this on the first post. Please help :)

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Try the things I mentioned in the 4th post:

Did you change the "Allow Any ROM Size for Recognition" setting?

Did you change your code to correctly say (* romstyle = "M9K" *) ? Your pasted code is using Verilog comments, which won't do anything.

If you do these things, it will work (at least it works for me...)