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Altera_Forum
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11 years ago

Verilog ROM code is not inferred as ROM block!!

I have written a verilog code for a ROM: module sync_rom (clock, address, data_out); input clock; input [3:0] address; output [31:0] data_out; reg [31:0] data_out;...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Most likely your problem is that each of your ROM instances which you hope would consume 512 bits is requiring either an entire M9K or one half of one M9K if the fitter successfully uses "Packed Mode" when fitting the ROMs together.

You can't really use "total bits" as an indicator of how much space you have remaining, because a design like yours could map very inefficiently and consume all of the M9K with very low total bit count. Look at the Fitter report in Fitter->Resource Section->Resource Usage Summary to get the high level number of M9K used/available.

You can read in some detail about memory resources in your device handbook (e.g. Cyclone III here http://www.altera.com/literature/hb/cyc3/cyc3_ciii51003.pdf with Packed Mode described on page 5).