Toplevel Simulation Control Signal And Retain Post-Fit Netlist

You could define a generic parameter in the entity like:

SIMULATION : std_logic := '1' ; -- chose '0' or '1' 

process( ... , SIMULATION , ... )
 begin
 . . .
  if (SIMULATION = '1') then
     counter <= SMALL ;
  else
    counter <= LARGE ;
  end if ;
 . . .

This problem with this is that the QuatusII compiler will optimise out the simulation control logic and that I am simulating the timing model i.e. post-fit netlist HDL output.

Generic will not help as it is settled per build.

[Kaz: Basstudio specifically mentioned he wants to avoid using a pin at all (and I mentioned that using a generic would optimize certain things away)]

Thanks guys.

Josyb:Apologies for missing the issue of pins.

To Kaz: sometimes we all are a bit quick, it has happened to me as well

Possibly now I understood the post, i.e. the rtl design itself must detect whether it is inside a testbench or inside the warm fpga...

signal reg1 : std_logic := '0';
signal reg2 : std_logic := '0';
process
begin
wait until clk = '1';
reg1 <= unused_pin;
if reg1 = '0' then
   reg2 <= '0';
end if;
end process;

I think this would still cause a problem in the target hardware if a virtual pin results in a floating input as you cannot guarantee the input level, thus this would be sampled and ripple through reg1->reg2-> to the simulation control signal.

Quartus will not assign virtual pins to any physical pin, as that would defeat the purpose of being virtual.

library altera ;
use altera.altera_syn_attributes.all ;
entity top is
 ...
 port (
  ...
  TestVirtualPin : in std_logic := '1' ;
  ...
  ) ;
  attribute altera_attribute of TestVirtualPin  : signal is "-name VIRTUAL_PIN on";
end entity