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Altera_Forum
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15 years ago

Toplevel Simulation Control Signal And Retain Post-Fit Netlist

I am working on a large CycloneIII design using QuartusII v9.0. In our design we have a toplevel input simulation control signal that is routed to various aspects of the design. This simulation...
Altera_Forum's avatar
Altera_Forum
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15 years ago

[Kaz: Basstudio specifically mentioned he wants to avoid using a pin at all (and I mentioned that using a generic would optimize certain things away)]

Now, if you simulate your design you use a testbench, I assume. I suppose you could define your simulate pin as virtual but connect it to '0' in the entity's port declaration. Your testbench can exercise that simulate pin to '1' and your simulation will run quicker. I believe this will work. but I have no idea what will happen on the PCB! The pin is virtual and 'initialised' to '0' so it should present a zero?