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Altera_Forum
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15 years ago

Toplevel Simulation Control Signal And Retain Post-Fit Netlist

I am working on a large CycloneIII design using QuartusII v9.0. In our design we have a toplevel input simulation control signal that is routed to various aspects of the design. This simulation...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

To Kaz: sometimes we all are a bit quick, it has happened to me as well

I thought Basstudio's idea was to be able to simulate with short times but when loading the logic in real hardware to work with the long times? Or are suggesting to set the register bit, via Nios or memory editor, during the simulation?