Toplevel Simulation Control Signal And Retain Post-Fit Netlist

Possibly now I understood the post, i.e. the rtl design itself must detect whether it is inside a testbench or inside the warm fpga...

I will try this (if I don't use any active pins): assign a spare unused pin to a register. Set the pin to '1' in the testbench. When the same design is downloaded inside fpga, hopefully the register will not be driven and so stay '0' at powerup.

I say hopefully because the pin will be floating and therefore may drive the register high. To work around this you may add further latching logic as follows:

signal reg1 : std_logic := '0';
signal reg2 : std_logic := '0';
process
begin
wait until clk = '1';
reg1 <= unused_pin;
if reg1 = '0' then
   reg2 <= '0';
end if;
end process;

thus reg2 should eventually become '0'