Toplevel Simulation Control Signal And Retain Post-Fit Netlist

You could define a generic parameter in the entity like:

SIMULATION : std_logic := '1' ; -- chose '0' or '1' 

and use the SIMULATION parameter to other logic like a normal signal.

process( ... , SIMULATION , ... )
 begin
 . . .
  if (SIMULATION = '1') then
     counter <= SMALL ;
  else
    counter <= LARGE ;
  end if ;
 . . .

Beware the compiler now has a 'fixed' value and will possibly optimize registers away, but the design will operate correctly.

If you want to retain the netlist with a selectable simulation signal, but don't want to use a pin for it, you have to find a way to set an internal register by using a few input signals in a combination that 'never' exists in nirmal operation.

Another idea might be to use the Data0 signal, in Passive Serial configuration (and possibly other modes too, but I never use those, so I don't know) you can declare Data0 to be used for logic after configuration, make it an input and keep it high or low.