Hello, I am using a Cyclone V device and have another external device that is supposed to take input from the FPGA and return a value to the FPGA where it is then latched. I have attached an diagram of the scenario below. What is the correct timing constraint to apply to properly constrain this? I was thinking about set_input_delay and set_output_delay, but I'm not sure how to extrapolate the required values since the input delay relies on the FPGA's internal propagation delay of the output and vice versa. That can't happen because those internal propagation delays are not known until fitting.Thank you

The internal delays would be set up based on the external delay. That's how set_input_delay and set_output_delay work. If you define the external delay with set_max_delay and set_min_delay, it should work the same way.

So the external device is just combinatorial logic or does it also have input and output registers?If it's just logic (not clocked), you could probably use set_max_delay and set_min_delay between the output and input ports to define all the external delay. Just add up the trace delays and tco (is it called tco in the device's spec but not clocked? Hmm.) to come up with values.Or are you saying that the FPGA clocks the external device which then sends a value back to the FPGA? In that case, that's a feedback design, so you'd need to define the output clock from the FPGA as a generated clock, set the output port as a false path so it is not analyzed as a data output, and use set_input_delay on the input, referencing the output clock and setting max/min values based on the total trace and tco delay through the external device.

Hi,For the synchronous I/O external device:Check this virtual class link https://learning.intel.com/Developer/learn/courses/841/intelr-quartusr-prime-pro-software-timing-analysis-part-4-io-interfaces/lessons/1506:99/intelr-quartusr-prime-pro-software-timing-analysis-part-4-io-interfaces (page 18-29) and this link https://community.intel.com/t5/FPGA-Wiki/Timing-Constraints/ta-p/735562 on set_input_delay and set_output_delay.For the constraints, just need to know the board delay(max/min), board clock skew(max/min) and external device's tsu, th, tco(max/min) will do. The FPGA's internal propagation delay will be handled and calculated by the tool itself.Thanks,Best Regards,Sheng

It is combinatorial logic. When using set_max_delay and set_min_delay between the ports, there isn't an internal path between the two. How does the max_delay then apply for that? I called it Tco because I was looking at Intel Design examples and all of the internal device delays were Tco so I decided to call it the same just to be consistent, doesn't really make sense in this case if you know what CO stands for.

Its not a synchronous IO Device, its combinatorial. Perhaps the usage of Tco in the external device is confusing. That is just the combinatorial propagation delay.

Timing constraints for external logic that takes input from, and outputs to an FPGA

15 Replies

sstrell
Super Contributor
2 years ago
So the external device is just combinatorial logic or does it also have input and output registers?
If it's just logic (not clocked), you could probably use set_max_delay and set_min_delay between the output and input ports to define all the external delay. Just add up the trace delays and tco (is it called tco in the device's spec but not clocked? Hmm.) to come up with values.
Or are you saying that the FPGA clocks the external device which then sends a value back to the FPGA? In that case, that's a feedback design, so you'd need to define the output clock from the FPGA as a generated clock, set the output port as a false path so it is not analyzed as a data output, and use set_input_delay on the input, referencing the output clock and setting max/min values based on the total trace and tco delay through the external device.
- TuckerZ
  Occasional Contributor
  2 years ago
  It is combinatorial logic.
  When using set_max_delay and set_min_delay between the ports, there isn't an internal path between the two. How does the max_delay then apply for that? I called it Tco because I was looking at Intel Design examples and all of the internal device delays were Tco so I decided to call it the same just to be consistent, doesn't really make sense in this case if you know what CO stands for.
  - ShengN_altera
    Super Contributor
    2 years ago
    [Edited]
    I think use set_max_delay and set_min_delay between the output and input ports means like below (tsu, th, tco(max/min) are external device value):
    Input Ports:
    set_max_delay -from [get_ports {<input>}] [board delay(max)+<Tco_Requirement>]
    set_min_delay -from [get_ports {< input >}] [board delay(min)+<MinTco_Requirement>]
    Output Ports:
    set_max_delay -to [get_ports {<output>}] [board delay(max)+<Tsu_Requirement>]
    set_min_delay -to [get_ports {<output>}] [board delay(min)-<Th_Requirement>]
ShengN_altera
Super Contributor
2 years ago
Hi,

For the synchronous I/O external device:
Check this virtual class link https://learning.intel.com/Developer/learn/courses/841/intelr-quartusr-prime-pro-software-timing-analysis-part-4-io-interfaces/lessons/1506:99/intelr-quartusr-prime-pro-software-timing-analysis-part-4-io-interfaces (page 18-29) and this link https://community.intel.com/t5/FPGA-Wiki/Timing-Constraints/ta-p/735562 on set_input_delay and set_output_delay.
For the constraints, just need to know the board delay(max/min), board clock skew(max/min) and external device's tsu, th, tco(max/min) will do. The FPGA's internal propagation delay will be handled and calculated by the tool itself.

Thanks,
Best Regards,
Sheng
- TuckerZ
  Occasional Contributor
  2 years ago
  Its not a synchronous IO Device, its combinatorial. Perhaps the usage of Tco in the external device is confusing. That is just the combinatorial propagation delay.
- TuckerZ
  Occasional Contributor
  2 years ago
  I haven't found an answer to this yet. Where else can I go for answers to this question? Is there someone at Intel that would know more?
- TuckerZ
  Occasional Contributor
  2 years ago
  I haven't found a solution to this. Where else might I go to find a solution? @ShengN_Intel
  - ShengN_altera
    Super Contributor
    2 years ago
    Hi @TuckerZ ,
    May be can try with these sdc constraints:
    set_input_delay (max) (tp2(max) + tco(max))
    set_input_delay (min) (tp2(min) + tco(min))
    set_output_delay (max) (tp1(max)) #since don't have tsu and th
    set_output_delay (min) (tp1(min)) #since don't have tsu and th
    Below sourced from this document https://web02.gonzaga.edu/faculty/talarico/CP430/LEC/TimeQuest_User_Guide.pdf (page 61)
    Combinatorial Paths through Device:
    set_max_delay -from [get_ports {<input>} -to [get_ports {<output>}] <Tpd_Requirement>
    set_min_delay -from [get_ports {<input>} -to [get_ports {<output>}] <minTpd_Requirement>
    Input Ports:
    set_max_delay -from [get_ports {<input>}] (tp2(max) + tco(max))
    set_min_delay -from [get_ports {< input >}] (tp2(min) + tco(min))
    Output Ports:
    set_max_delay -to [get_ports {<output>}] (tp1(max)) #since don't have tsu and th
    set_min_delay -to [get_ports {<output>}] (tp1(min)) #since don't have tsu and th
    Note: SDC constraints above use external timing parameters.
sstrell
Super Contributor
2 years ago
I was thinking using -from the output and -to the input in the same constraint. Just add up the loop delays (trace + "tco") and use as the value. You don't need to know/use a th or tsu for this.
- TuckerZ
  Occasional Contributor
  2 years ago
  Does the program apply the constraint in the way I want it to? Will the timing analyzer "create" a timing path between those two ports that allows the program to use both internal delays during an individual calculation?
  For example, Let's say there is
  A generated internal output delay of 2ns
  A total external propagation delay of 3ns
  And a generated internal input delay of 1ns
  Would the program be able to recognize that it needs to add the 1ns from the input to the output's max_delay calculation for a total of 6ns?
  Thank you for all the information so far,
  Tucker Zischka
  - sstrell
    Super Contributor
    2 years ago
    The internal delays would be set up based on the external delay. That's how set_input_delay and set_output_delay work. If you define the external delay with set_max_delay and set_min_delay, it should work the same way.

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Timing constraints for external logic that takes input from, and outputs to an FPGA

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