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TuckerZ's avatar
TuckerZ
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Timing constraints for external logic that takes input from, and outputs to an FPGA

Hello, I am using a Cyclone V device and have another external device that is supposed to take input from the FPGA and return a value to the FPGA where it is then latched. I have attached an diagra...
Timing
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
1 year ago

I was thinking using -from the output and -to the input in the same constraint. Just add up the loop delays (trace + "tco") and use as the value. You don't need to know/use a th or tsu for this.