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TuckerZ's avatar
TuckerZ
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Timing constraints for external logic that takes input from, and outputs to an FPGA

Hello, I am using a Cyclone V device and have another external device that is supposed to take input from the FPGA and return a value to the FPGA where it is then latched. I have attached an diagra...
Timing
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,


For the synchronous I/O external device:

Check this virtual class link https://learning.intel.com/Developer/learn/courses/841/intelr-quartusr-prime-pro-software-timing-analysis-part-4-io-interfaces/lessons/1506:99/intelr-quartusr-prime-pro-software-timing-analysis-part-4-io-interfaces (page 18-29) and this link https://community.intel.com/t5/FPGA-Wiki/Timing-Constraints/ta-p/735562 on set_input_delay and set_output_delay.

For the constraints, just need to know the board delay(max/min), board clock skew(max/min) and external device's tsu, th, tco(max/min) will do. The FPGA's internal propagation delay will be handled and calculated by the tool itself.


Thanks,

Best Regards,

Sheng


TuckerZ's avatar
TuckerZ
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Its not a synchronous IO Device, its combinatorial. Perhaps the usage of Tco in the external device is confusing. That is just the combinatorial propagation delay.