Occasional Contributor
Super ContributorSo the external device is just combinatorial logic or does it also have input and output registers?
If it's just logic (not clocked), you could probably use set_max_delay and set_min_delay between the output and input ports to define all the external delay. Just add up the trace delays and tco (is it called tco in the device's spec but not clocked? Hmm.) to come up with values.
Or are you saying that the FPGA clocks the external device which then sends a value back to the FPGA? In that case, that's a feedback design, so you'd need to define the output clock from the FPGA as a generated clock, set the output port as a false path so it is not analyzed as a data output, and use set_input_delay on the input, referencing the output clock and setting max/min values based on the total trace and tco delay through the external device.
Occasional ContributorIt is combinatorial logic.
When using set_max_delay and set_min_delay between the ports, there isn't an internal path between the two. How does the max_delay then apply for that? I called it Tco because I was looking at Intel Design examples and all of the internal device delays were Tco so I decided to call it the same just to be consistent, doesn't really make sense in this case if you know what CO stands for.
Super Contributor[Edited]
I think use set_max_delay and set_min_delay between the output and input ports means like below (tsu, th, tco(max/min) are external device value):
Input Ports:
set_max_delay -from [get_ports {<input>}] [board delay(max)+<Tco_Requirement>]
set_min_delay -from [get_ports {< input >}] [board delay(min)+<MinTco_Requirement>]
Output Ports:
set_max_delay -to [get_ports {<output>}] [board delay(max)+<Tsu_Requirement>]
set_min_delay -to [get_ports {<output>}] [board delay(min)-<Th_Requirement>]
Super ContributorI think you may ignore the above as combinatorial logic don't have tsu and th. Sorry for confusing
