TuckerZ
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Looking for Cyclone V Triple Speed Ethernet (TSE) SGMII Example Design Files
Hello, I am looking for example design files for adapting to SGMII using Intel's Triple Speed Ethernet (TSE) in Cyclone V devices. I was reading Application Note 796 (Section 4.5.1.2.4) where it said to refer to the example design to see an example of adapting the HPS's EMAC to SGMII. The example design is on RocketBoard. It contains a broken link to the FPGA files (cv_soc_sgmii_ed.tar.gz) of the example design. Does anyone have or know where to find these files? Has this been uploaded somewhere else? Is there someone or someplace else I should ask this question to? I want to specifically see what the SDC file looks like. Thank you, TuckerZSolved580Views0likes5CommentsLooking for Cyclone V Triple Speed Ethernet (TSE) SGMII Example Design Files
Hello, I am looking for example design files for adapting to SGMII using Intel's Triple Speed Ethernet (TSE) in Cyclone V devices. I was reading Application Note 796 (Section 4.5.1.2.4) where it said to refer to the example design to see an example of adapting the HPS's EMAC to SGMII. The example design is on RocketBoard. It contains a broken link to the FPGA files (cv_soc_sgmii_ed.tar.gz) of the example design. Does anyone have or know where to find these files? Has this been uploaded somewhere else? Is there someone or someplace else I should ask this question to? I want to specifically see what the SDC file looks like. Thank you, TuckerZSolved772Views0likes4CommentsRe: Timing constraints for external logic that takes input from, and outputs to an FPGA
Typed the command twice. The first is the correct one. Yes, thank you for the corrections. It is even worse than what I originally typed out. The implementation details are not of importance since I am working on those still. The tool should have certainly caught the timing issues at this point considering such abysmal timing. The tool does say these I/O are unconstrained. I'm not sure the set_max_delay command did what I wanted it to do considering it didn't catch this. Any Insight? set_max_delay -from [get_ports output_port] -to [get_ports input_port] 10.3684.2KViews0likes0CommentsRe: Timing constraints for external logic that takes input from, and outputs to an FPGA
I added the following constraints. set_max_delay -from [get_ports output_port] -to [get_ports input_port] 10.368 set_max_delay -from [get_ports output_port] -to [get_ports input_port] 0 After rerunning compilation and checking timing, Delays and the Clock Skews for the Registers immediately before the output ports and after the input ports are as follows: Clock Delay for the output register is 8.263ns The data delay from the output register to the output port is 8.302ns The maximum external propagation delay is 10.368ns Clock Delay for the input register is 7.773ns The data delay from the input port to the input register is 9.817ns The clock is running at 120MHz = 8.333ns The question is, what kind of analysis is being performed on this path now? The ports are currently unconstrained so it is not doing a synchronous analysis. Doing the math here, there is a negative slack of: Data Required Time - Data Arrival Time = Slack (8.333+7.773+9.817) - (8.263+8.302+10.368 ) = -1.01ns It's not doing that analysis nor reporting the "violation". I expect it to report the violation because the maximum external delay would cause the data to arrive after the latch clock edge.4.3KViews0likes2Comments