Occasional Contributor
Super ContributorHi,
For the synchronous I/O external device:
Check this virtual class link https://learning.intel.com/Developer/learn/courses/841/intelr-quartusr-prime-pro-software-timing-analysis-part-4-io-interfaces/lessons/1506:99/intelr-quartusr-prime-pro-software-timing-analysis-part-4-io-interfaces (page 18-29) and this link https://community.intel.com/t5/FPGA-Wiki/Timing-Constraints/ta-p/735562 on set_input_delay and set_output_delay.
For the constraints, just need to know the board delay(max/min), board clock skew(max/min) and external device's tsu, th, tco(max/min) will do. The FPGA's internal propagation delay will be handled and calculated by the tool itself.
Thanks,
Best Regards,
Sheng
Occasional ContributorI haven't found a solution to this. Where else might I go to find a solution? @ShengN_Intel
Super ContributorHi @TuckerZ ,
May be can try with these sdc constraints:
set_input_delay (max) (tp2(max) + tco(max))
set_input_delay (min) (tp2(min) + tco(min))
set_output_delay (max) (tp1(max)) #since don't have tsu and th
set_output_delay (min) (tp1(min)) #since don't have tsu and th
Below sourced from this document https://web02.gonzaga.edu/faculty/talarico/CP430/LEC/TimeQuest_User_Guide.pdf (page 61)
Combinatorial Paths through Device:
set_max_delay -from [get_ports {<input>} -to [get_ports {<output>}] <Tpd_Requirement>
set_min_delay -from [get_ports {<input>} -to [get_ports {<output>}] <minTpd_Requirement>
Input Ports:
set_max_delay -from [get_ports {<input>}] (tp2(max) + tco(max))
set_min_delay -from [get_ports {< input >}] (tp2(min) + tco(min))
Output Ports:
set_max_delay -to [get_ports {<output>}] (tp1(max)) #since don't have tsu and th
set_min_delay -to [get_ports {<output>}] (tp1(min)) #since don't have tsu and th
Note: SDC constraints above use external timing parameters.
