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ShengN_altera

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Joined 4 years ago

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Re: Setup slack violations?
Seems like both the launch and latch clocks are asynchronous which causes the cdc with high clock skew. Please refer this link https://www.intel.com/content/www/us/en/docs/programmable/683243/22-4/constraining-cdc-paths.html for constraining cdc path.
12 hours ago Place Quartus® Prime
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Re: MAX 10. No 3.0 V Schmitt Trigger I/O standard
May I know which output voltage do you mean?
12 hours ago Place FPGA Device
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Re: Agilex 5 A5EC065BB32AE5SR0 issue
You'll have to use pll clock source with low jitter check this link Schematic can be downloaded from installer package link For example premium dev kit, I set the location as below: Signal tap result: I use issp to toggle the reset: issp u0 ( .source (sys_reset) // output, width = 1, sources.source );
2 days ago Place FPGA Device
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Re: MAX 10. No 3.0 V Schmitt Trigger I/O standard
According to the document screenshot: Yes, MAX 10 don't support 3.0 V Schmitt Trigger. I think you can use 2.5V for both Schmitt Trigger and slew rate control.
3 days ago Place FPGA Device
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Re: Quartus Academic program licence
The latest email is mailto:university@altera.com Could you follow up again with that email?
12 days ago Place Quartus® Prime
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Re: Cyclone V Emulated LVDS Signal Voltages
Kindly confirm whether the suggested steps have addressed your concern?
23 days ago Place FPGA Device
56Views
1like
1Comment
Re: Quartus Academic program licence
Please submit a request through here https://www.intel.com/content/www/us/en/developer/topic-technology/fpga-academic/support.html
23 days ago Place Quartus® Prime
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2Comments
Re: Clock switchover on CycloneV PLL
It would take 2-3 clock cycles to detect the stopped clock: This is not mentioned in the document. another 2-3 clock cycles to complete the switch: This is mentioned in https://www.intel.com/content/www/us/en/docs/programmable/683359/17-0/ip-core-parameters-clock-switchover-tab.html the circuit automatically switches to the backup clock in a few clock cycles a couple of cycles extra until the PLL achieves lock: This is mentioned in https://www.intel.com/content/www/us/en/docs/programmable/683359/17-0/pll-lock.html The number of cycles required to gate the lock signal depends on the PLL input clock which clocks the gated-lock circuitry. Divide the maximum lock time of the PLL by the period of the PLL input clock to calculate the number of clock cycles required to gate the lock signal. The Max Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) is 1 ms based on this https://www.intel.com/content/www/us/en/docs/programmable/683801/current/pll-specifications.html
25 days ago Place FPGA Device
10Views
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Re: Clock switchover on CycloneV PLL
Yes, if based on this internal message: It would take 2-3 clock cycles to detect the stopped clock , another 2-3 clock cycles to complete the switch and a couple of cycles extra until the PLL achieves lock.
25 days ago Place FPGA Device
66Views
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Re: Quartus GUI License Error
Try re-generate the questa license and make sure nic id is correct. Also try with SALT_LICENSE_SERVER environment variable (fixed license). If still cannot, use float license and set up license server using daemon. Related KDB link https://www.intel.com/content/www/us/en/support/programmable/articles/000099465.html
25 days ago Place Quartus® Prime
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