ShengN_alteraSuper ContributorJoined 4 years ago1754 Posts110 LikesLikes received159 SolutionsView All Badges
ContributionsMost RecentMost LikesSolutionsRe: Quartus Pro 25.3 crash using rhel7/8 Hi, Internal message as below: There was a Quartus Prime Pro issue broadly discovered by customers, field and internal teams in which the Quartus code that calculates the date and time from the DDM client ID mistakenly identifies the time being shifted an hour from the current time which in turn, causes a Quartus crash to take place. This issue began when the year turned to 2026 and we moved to a two-digit date in the month of January. This crash affects: Quartus Prime Pro Software versions v23.3 through v25.3.1 Quartus Embedded Edition v25.3 and v25.3.1 Quartus Programmer v23.3 through v25.3.1 This issue can be seen when using Quartus software through command line or GUI interface. Quartus Patch requests have been filed for the above software and tools. A KDB draft is available and will be reviewed and released when the patches are ready. These fixes and KDB are being driven with utmost priority. Will get back once the patch and kdb are available. Re: Trying to print warning messages from tcl build script I believe you're using Standard version. If check Standard version document https://docs.altera.com/r/docs/683325/18.1/intel-quartus-prime-standard-edition-user-guide-scripting/command-line-scripting There's neither get_messages nor get_message_count command. Also get_message_count is for pro version only. Re: Quartus Prime Pro Hierarchy View has blank rows for some instances May I know any further update or concern from your side? Re: Signal counts incorrectly on EP4CE6E22C8N while others signal work fine (same code Verilog) May I know which signal is correct and which signal is problem one? Re: Address Space? Understood that. I just want to confirm that those two bits are byte offset or not? Or could you remove the Nios V connection from arbiter module and just connect custom hdl, what happen to the min address width? Re: Address Space? I mean if you don't use the arbiter module but straight connect both Nios V and custom HDL to sdram what happen to the minimum address width? You can use platform designer arbitration logic https://docs.altera.com/r/docs/683609/25.1.1/quartus-prime-pro-edition-user-guide-platform-designer/arbitration Re: Address Space? May I know if the arbiter module is not used, the custom hdl min address width is? Re: Address Space? [DELETED] Re: Agilex 5 IOPLL Max Numbers and Tool Display Mismatch Thanks for the confirmation. I'll close the ticket. Re: Agilex 5 IOPLL Max Numbers and Tool Display Mismatch Interal response below: Looking at the device dump, I can confirm the SM4 device has 11 IO PLLs. It is safe to ignore the 25.1 report. You may ignore the report.