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ShengN_altera
Joined 4 years ago
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Re: My signaltap test has some problem
Hi, The gap is normal behaviour. I test the example design with don't care triggering points and i get gap like below: When I set the rising edge triggering points like below: In first picture, there's no trigger point (don't care) so the 0 is at the beginning. In second picture, the rising edge trigger point is being set and the 0 is at the rising edge and there's waveform at the negtive time frame before 0. The gap mean there's no waveform at that point. The gap will be reduced if the sample depth is reduced. Your case most likely due to the trigger point (once per program) had been passed. May I know which triggering you expect? Please check also the timing whether it's clean and whether the tapping signals having common sampling clock as mentioned by FvM0Views0likes1CommentRe: Error ID 18694: Still not resolved ???
Hi EVAN This had been sync internally that this is not a bug. The LVDS receiver all mode including Soft-CDR cannot have reference clock cross I/O bank. There's confusion at the document for user and update to the document is in the process. By the way, the Soft-CDR mode uses DPA block as well.13Views0likes0Comments