Timing constraints for external logic that takes input from, and outputs to an FPGA

Hi @TuckerZ ,

May be can try with these sdc constraints:

set_input_delay (max) (tp2(max) + tco(max))

set_input_delay (min) (tp2(min) + tco(min))

set_output_delay (max) (tp1(max)) #since don't have tsu and th

set_output_delay (min) (tp1(min)) #since don't have tsu and th

Below sourced from this document https://web02.gonzaga.edu/faculty/talarico/CP430/LEC/TimeQuest_User_Guide.pdf (page 61)

Combinatorial Paths through Device:
set_max_delay -from [get_ports {<input>} -to [get_ports {<output>}] <Tpd_Requirement>

set_min_delay -from [get_ports {<input>} -to [get_ports {<output>}] <minTpd_Requirement>

Input Ports:
set_max_delay -from [get_ports {<input>}] (tp2(max) + tco(max))
set_min_delay -from [get_ports {< input >}] (tp2(min) + tco(min))
Output Ports:
set_max_delay -to [get_ports {<output>}] (tp1(max)) #since don't have tsu and th
set_min_delay -to [get_ports {<output>}] (tp1(min)) #since don't have tsu and th

Note: SDC constraints above use external timing parameters.