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TuckerZ's avatar
TuckerZ
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Timing constraints for external logic that takes input from, and outputs to an FPGA

Hello, I am using a Cyclone V device and have another external device that is supposed to take input from the FPGA and return a value to the FPGA where it is then latched. I have attached an diagra...
Timing
TuckerZ's avatar
TuckerZ
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Does the program apply the constraint in the way I want it to? Will the timing analyzer "create" a timing path between those two ports that allows the program to use both internal delays during an individual calculation?

For example, Let's say there is

  • A generated internal output delay of 2ns
  • A total external propagation delay of 3ns
  • And a generated internal input delay of 1ns

Would the program be able to recognize that it needs to add the 1ns from the input to the output's max_delay calculation for a total of 6ns?

Thank you for all the information so far,

Tucker Zischka

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
1 year ago

The internal delays would be set up based on the external delay. That's how set_input_delay and set_output_delay work. If you define the external delay with set_max_delay and set_min_delay, it should work the same way.