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Honored ContributorSystem Verilog: Can´t change value of a "struct" variable
Hi,
I´m newbie on Verilog, actually also in System Verilog, but worked long time ago with VHDL and C++ languages. I used a template of a Moore state machine from ALTERA for Verilog, and performed some changes in order to start the learning. However, during simulation, I can´t see any change at both the variables currentstate.level_main and currentstate.level_sub. I took the care to perform reset during simulation.module moore_mac
(
input clk, data_in, reset,
output reg data_out
);
reg sub_state3, state ;
parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011 ;
parameter S3_0 = 3'b100, S3_1 = 3'b101, S3_2 = 3'b110 ;
typedef enum { SM0 , SM1 , SM2 , SM3 } STATE_MACHINE ;
typedef enum { SM0_S, SM1_S, SM2_S, SM3_S } STATE_MACHINE_S ;
typedef struct {
reg Level_main ;
reg Level_sub ;
} FSM ;
FSM CurrentState ;
// Determine the next state
always @ ( posedge clk or posedge reset )
begin
if (reset)
begin
state <= S1 ;
sub_state3 <= S3_0 ;
CurrentState.Level_main <= S0 ;
CurrentState.Level_sub <= S3_0 ;
end
else
case (state)
S0:
state <= S1;
S1:
if (data_in) state <= S1;
else state <= S2;
S2:
if (data_in) state <= S1;
else state <= S3;
S3:
state <= next_state ( sub_state3 ) ;
endcase
end
// Output depends only on the current state
always @ (state)
begin
case (state)
S0:
data_out = S0 ;
S1:
data_out = S1 ;
S2:
data_out = S2 ;
S3:
data_out = S3 ;
default:
data_out = S0 ;
endcase
end
// *******************************************************
// Gets next state, by assessing corresponding sub_state
// *******************************************************
function next_state ;
input reg valSubstateBefore ;
reg valSubstateAfter ;
if ( valSubstateBefore < S3_2 )
begin
valSubstateAfter = valSubstateBefore + 1 ;
state = state ;
end
else
begin
valSubstateAfter = S3_0 ;
state = S0 ;
end
sub_state3 = valSubstateAfter ;
next_state = state ;
endfunction
// *******************************************************
endmodule
