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Hi Tricky,
Thanks for the quick reply; I changed the function declaration with the improvements that you suggested, and in fact now its constructs appears much more consistent with a good coding practice than the one I posted earlier; I´m coding based on several examples spread on the Web what explains the old style.
However after compiling the changes on the function...
...occurred the error highlighted on header above, which I could not determine how to fix it, although some most recent researches on the web.
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try putting the [] after the function parameter.
(logic valStateBefore[2:0],...)
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With respect to Modelsim, I have not given up, I really need a more powerful tool, and have to solve the problem of installation, but I'm trying to compile the code in the meantime.
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You will struggle to find one, modelsim is one of the most powerful simulators out there. You might use NCSim if you're doing asics, but modelsim has all sorts of features quartus and vivado (xilinx equivolent tool) will never have:
RTL Simulation
Gate level simulation
Code coverage
Mixed langauge simulation
Design Profilers
SV Assertions
UVM Support
ETc etc.
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Ok, I had wrongly employed the term
instantiation when I was actually referring to
function call.
Anyway, it was not what I done at the line 71 of the code posted above ?
currentstate <= next_state ( ... ) ; --- Quote End ---
No, this is just calling next_state function. You code has no instantitation.
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As I mentioned before, this is just a preliminary draft of a code whose purpose is to work as a template to a state machine which will work with 2 levels of states. Once the current state falls into certain states, there must run other another levels of state machines ( which I named as substates ).
The application which is currently working, was wrote in C language and has
dozens of states. In order to achieve a clean and structured code, I was wondering if I could create a skeleton for the code which would work as a template to insert the remaining system behaviors. Someone could suggest to me adopt a better approach such as using IP cores, but the purpose of such a development is mainly learning of the SV language features.
Once again, thanks for the assistance.
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This kind of explains alot. Direct ports of C to HDL never really work very well. It would be much better to try and re-enginner the system for a hardware platform.
What are the end-goals? What is the source data?
Have you got a circuit diagram of your intended architecture? This should be the first step before writing any HDL (its a description language after all, without the circuit, how do you expect to describe it?)
As to this example, I would suggest forgetting about functions. Functions and tasks in HDL should only really be used to tidy away code that is repeated over and over. Given your description, I would forget about having a struct with two states, just have two discrete variables. Have one working in one always block, and the second in another always block that is only active when the first is in the correct state:
always @(posedge clk)
begin
// Main state machine
end
always @(posedge clk)
begin
if (main_state == correct_state) begin
//sub sstate machine
end
end
But Persoanlly, I think a re-design is in order, as it is very rare that you need two state machines. Maybe you need two modules that handle two separate things?
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