System Verilog: Can´t change value of a "struct" variable

I´m currently using the structure bellow at a function that handles both its inputs and outputs as type fsm_t.

	typedef struct packed { 
	   bit  Level_main_t ;
	   bit  Level_sub_t ;
	   bit  Level_subcurr_t ;
	} FSM_t ;

That is something like that:

function   FSM_t  next_state ( input ...)
        FSM_t next_state_return ;
        ...
        return next_state_return ;
endfunction

Once I need to use at the block a reg variable having the same format to exchange values, I performed the following :

	typedef struct packed { 
	   reg  Level_main ;
	   reg  Level_sub ;
	   reg  Level_subcurr ;
	} FSM ;

...and created the variable bellow:

FSM 	 StateMachine 	;  

However, I don´t like the above code arrangement, due I employed a structure duplicated with the same format.

Does it have any way to perform such a declaration on a smarter way, as for example with only the type fsm_t ?